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ICS507-01/02 PECL Clock Synthesizer
Description
The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-LockedLoop (PLL) techniques, the devices use a standard fundamental mode crystal to produce output clocks up to 200 MHz. Stored in each chip's ROM is the ability to generate a selection of different multiples of the input reference frequency, including an exact 155.52 MHz clock from common crystals. For lowest jitter and phase noise on a 155.52 MHz clock, a 19.44 MHz crystal and the x8 selection can be used.
Features
* Packaged as 16 pin narrow SOIC or die * Input crystal frequency of 5 - 27 MHz * Input clock frequency of 5 - 52 MHz * Uses low-cost crystal * Differential PECL output clock frequencies up to 200 MHz * Duty cycle of 49/51 * 3.3 V or 5.0 V10% operating supply * Ideal for SONET applications and oscillator manufacturers * Advanced, low power CMOS process * Industrial temperature versions available
Block Diagram
GND
VDD
1.1k RES
270
S0:1
2 Clock Synthesis and Control Circuitry
Clock Buffer/ Crystal Oscillator
Output Buffer 62
PECL
VDD 62
Crystal or clock
X1
Output Buffer
PECL
270
X2
Output resistor values shown are for unterminated lines. Refer to MAN09 for additional information.
Output Enable (both outputs)
1 Revision 042600 Printed 11/13/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126* (408)295-9800tel * www.icst.com
MDS 507 C
ICS507-01/02 PECL Clock Synthesizer
Pin Assignment ICS507-01/02
X1/ICLK VDD VDD S1 GND GND NC PECL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 NC S0 OE NC NC RES PECL
Clock Multiplier Select Table
S1 0 0 0 M M M 1 1 1 S0 0 M 1 0 M 1 0 M 1 Multiplier 9.72X* 10X 12X 6.25X 8X 5X 2X 3X 4X
*Use this selection to get 155.52 MHz from a 16 MHz input. For lowest phase noise generation of 155.52 MHz, use a 19.44 MHz crystal and the 8X selection.
16 pin narrow (150 mil) SOIC Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name X1/ICLK VDD VDD S1 GND GND NC PECL PECL RES NC NC OE S0 NC X2 Type XI P P TI P P O O I I TI XO
0 = connect pin directly to ground 1 = connect pin directly to VDD M = leave unconnected (floating)
Description Crystal or clock connection. Connect to a fundamental parallel mode crystal, or clock. VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3. VDD. Connect to VDD on pin 2. Decouple with pin 5. Multiplier select pin 1. Determines output frequency per table above. Connect to ground. Connect to ground. No connect. Nothing is connected internally to this pin. PECL Output. Connect to resistor load as shown on page one. Complementary PECL Output. Connect to resistor load as shown on page one. Bias Resistor Input. Connect a resistor between this pin and VDD. No connect. Nothing is connected internally to this pin. No connect. Nothing is connected internally to this pin. Output Enable. Tri-states both outputs when low. Internal pull-up. Multiplier select pin 0. Determines output frequency per table above. No Connect. Nothing is connected internally to this pin. Cr stal connection. Connect to cr stal, or leave unconnected for clock input.
Key: I=Input, O=output, TI=tri-level input, P=power supply connection; XI, XO=crystal connections
2 Revision 042600 Printed 11/13/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126* (408)295-9800tel * www.icst.com
MDS 507 C
ICS507-01/02 PECL Clock Synthesizer
Electrical Specifications
Parameter Conditions Minimum Typical ABSOLUTE MAXIMUM RATINGS (stresses be ond these can permanentl damage the device) T e m a Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Output Referenced to GND -0.5 Ambient Operating Temperature r ICS507M-0x 0 ICS507M-0xI -40 Soldering Temperature Max of 20 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted) D l Operating Voltage, VDD 3.0 Input High Voltage, VIH ICLK only VDD/2 + 1 VDD/2 Input Low Voltage, VIL ICLK only VDD/2 Input High Voltage, VIH S0, S1 VDD-0.5 Input Low Voltage, VIL S0, S1 Output High Voltage, VOH Note 2 VDD-1.2 Output Low Voltage, VOL Note 2 IDD Operating Suppl Current, note 3 No Load, 155.52MHz 67 Internal Cr stal Capacitance, X1 and X2 Pins 1, 8 26 Input Capacitance S0, S1 4 AC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted) D l Input Crystal Frequency 5 Input Clock Frequency 5 Output Frequency, ICS507-01 0 to 70C VDD = 5.0 V 10 0 to 70C VDD = 3.3 V 10 Output Frequency, ICS507-01I -40 to 85C VDD = 3.3 V or 5.0 V 10 Output Frequency, ICS507-02I 0 to 70C VDD = 5.0 V 125 0 to 70C VDD = 3.3 V 125 -40 to 85C VDD = 3.3 V or 5.0 V 125 Output Clock Duty Cycle 49 PLL Bandwidth 10 Absolute Clock Period Jitter Deviation from mean 75 One Sigma Clock Period Jitter 20 Notes: Maximum 7 VDD+0.5 VDD+0.5 70 85 260 150 5.5 VDD/2-1 VDD+0.5 VDD-2.0 Units V V V C C C C V V V V V V V mA pF pF MHz MHz MHz MHz MHz MHz MHz MHz % kHz ps ps
27 52 200 156 125 200 200 160 51
1) All typical values are at 5.0 V and 25C unless otherwise noted. 2) VOH and VOL can be set by the external resistor values on the PECL outputs. 3) IDD includes the current through the external resistors, which can be modified. 4) The phase relationship between input and output can change at power up. For a fixed phase relationship, see one of the ICS zero delay buffers.
3 Revision 042600 Printed 11/13/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126* (408)295-9800tel * www.icst.com
MDS 507 C
ICS507-01/02 PECL Clock Synthesizer
Applications
High Frequency Differential PECL Oscillators: The ICS507 plus a low frequency, fundamental mode crystal can build a high frequency differential output oscillator. For example, a 10 MHz crystal connected to the ICS507 with the 12X output selected (S1=0, S0=1) produces a 120 MHz PECL output clock. High Frequency TCXO: Extending the previous application, an inexpensive, low frequency TCXO can be built and the output frequency can be multiplied using the ICS507. Since the output of the chip is phaselocked to the input, the ICS507 has no temperature dependence, and the temperature coefficient of the combined system is the same as that of the low frequency TCXO. High Frequency VCXO: The bandwidth of the PLL is guaranteed to be greater than 10 kHz. This means that the PLL will track any modulation on the input with a frequency of less than 10 kHz. By using this property, a low frequency VCXO can be built, and the output can then be multiplied with the ICS507 to give a high frequency output, thereby producing a high frequency VCXO.
Decoupling and External Components
The ICS507 requires a 0.01F decoupling capacitor to be connected between VDD and GND on pins 2 and 5. It must be connected close to the ICS507. Other VDD and GND connections should be connected to those pins, or to the VDD and GND planes on the board. A resistor must be connected between the RES (pin 10) and VDD. Another four resistors are needed for the PECL outputs as shown on the block diagram on page 1. Suggested values of these resistors are shown in the Block Diagram, but they can be varied to change the differential pair output swing, and the DC level; refer to MAN09.
4 Revision 042600 Printed 11/13/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126* (408)295-9800tel * www.icst.com
MDS 507 C
ICS507-01/02 PECL Clock Synthesizer
Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Symbol A
A1
E
INDEX AREA
H
B
C
1
2
D A1 e C
h x 45
D E e H h L
Inches h Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 .050 BSC S 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500
Millimeters m Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 9.80 10.00 3.80 4.00 1.27 BSC S 5.80 6.20 0.25 0.50 0.41 1.27
A L
B
Ordering Information
Part/Order Number ICS507M-01 ICS507M-01T ICS507M-01I ICS507M-01IT ICS507-01-DSW ICS507-01-DPK ICS507-01-DWF ICS507M-02I ICS507M-02IT Marking Package Temperature 0 to 70C 0 to 70C -40 to 85C -40 to 85C 0 to 70C 0 to 70C 0 to 70C -40 to 85C -40 to 85C Minimum Quantities
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ICS507M-01 16 pin narrow SOIC ICS507M-01 16 pin SOIC on tape and reel ICS507M-01I 16 pin narrow SOIC ICS507M-01I 16 pin SOIC on tape and reel Probed wafers, cut, on sticky tape Tested die in waffle pack Die on uncut, probed wafers ICS507M-02I 16 pin narrow SOIC ICS507M-02I 16 pin SOIC on tape and reel
2500 pieces
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2500 pieces 1 wafer 1000 pieces 1 wafer
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2500 pieces
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
5 Revision 042600 Printed 11/13/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA *95126* (408)295-9800tel * www.icst.com
MDS 507 C

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